Location- Bangalore/ Noida/ Hyderabad 4 years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff. USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analy?